From April 26-28, the world’s first three-day SmartNICs Summit was held in Silicon Valley in the USA. More than 100 companies in the global SmartNICs field, including Intel, AMD, NVIDIA, and other internationally renowned companies, attended the summit.

Corigine was invited to participate in the keynote speech and announced the fourth generation architecture of Corigine’s ‘SmartNICs’ for the first time. Jim Finnegan, former VP of Intel and Corigine’s Executive VP since the beginning of this year, said: “SmartNICs provide a higher levels of scalability, flexibility and performance for today’s networks, and Corigine’s fourth generation DPU-based SmartNICs are highly programmable and extremely flexible, adaptable to application scenarios and tailored to different customers.

External ML/storage acceleration without server involvement, MMD design that supportslarge-scale parallel processing, link speeds increased to 200-400 Gbps, SW programmability, and hardware flexibility are all features of the fourth generation architecture of Corigine’s SmartNICs.

Since 2019, the R&D team of Corigine’s SmartNICs has been deployed globally, including Shanghai and Nanjing in China, Silicon Valley in the US, Cape Town and Centurion in South Africa. Corigine R&D teams from all over the world provide support for the continuous upgrading and optimization of Corigine’s SmartNICs in different fields. Finally, a complete DPU ecosystem from DPU chips to upper-layer applications has been formed, and with powerful hardware offloading capabilities and flexible programmability capabilities, it is valuable to customers in different industries and fields.