Corigine Agilio LX 40 and 100GbE SmartNICs incorporate two PCIe Gen3 x8 interfaces, 8GB of low-latency DDR3 memory, and 960 highly threaded flow processing cores that run accelerated Linux, Open vSwitch and DPDK code. Efficient use of dual-PCIe with multi-threaded memory and hardware accelerator access enable significantly greater NUMA performance in multi-socket systems. The following SmartNIC configurations are supported:
Datapath Offload | Network Acceleration and Offload
| Acceleration of Compute-intensive Functions |
Operating Systems |
Agilio LX 2x40GbE SmartNICs utilize the Agilio software solution to deliver higher application performance by accelerating Open vSwitch (OVS) and DPDK based networking datapaths while freeing up valuable CPU cycles. For network-port-to-VM traffic, it delivers 40Gbps line rate throughput at 128B packets while consuming less than 2 CPU cores. It can reach 50Gb/s line rate for 1000B packets. For network-port-to-network-port traffic that is more suitable for many service node applications, it delivers 80Gb/s line rate throughput at 500B packets while consuming less than 2 CPU cores. The Agilio LX 1x100GbE SmartNIC solution delivers 100Gb/s line rate throughput at 500B packets while consuming less than 2 CPU cores.
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