Responsibilities

1. Design: Work on USB3.2 IP uArch creation, design implementation, verification, FPGA timing closure

2. Verification: Work on USB3.2 IP UVM based verification environment set up, testcase creation and debug, regression and coverage work 

Requirements

1. Work with Design team to complete IP/ASIC production verification tasks

2. More than 5 years IP, ASIC or FPGA products verification experience

3. Should be able to build verification environment from scratch, set testplan base on project schedule and resource

4. Should be able to guide junior engineer to boost verification tasks

5. Should be proficient in coverage oriented random test with System Verilog and UVM

6. Should have hands on experience with shell/perl/makefile

7. Familiar with PCIE/USB/SATA/ethernet or other connectivity protocols is a plus

8. Good communication and problem solving skills

9. MS in Electrical Engineering